Image sensor including MRAM (magnetic random access memory)

ABSTRACT

A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No.10-2017-0006285, filed on Jan. 13, 2017, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

BACKGROUND

The inventive concept relates to an image sensor, such as acomplementary metal-oxide semiconductor (CMOS) image sensor, having astacked structure in which two semiconductor chips are bonded to eachother.

Generally, a CMOS image sensor (CIS) may include a pixel area and alogic area. In the pixel area, a plurality of pixels are arranged in atwo-dimensional array structure, wherein each pixel includes aphotodiode and several pixel transistors. The pixel transistors mayinclude, for example, a transfer transistor, a reset transistor, asource follower transistor, and a selecting transistor. Logic circuitsfor processing pixel signals from the pixel area may be arranged in thelogic area. Recently, a CIS has been developed where a pixel area isformed on one chip and a logic area is formed on another chip and thetwo chips are stacked together. A CIS having such a stacked structuremay provide images with high image quality due to, for example, beingable to increase of the number of pixels in the pixel area withoutdecreasing their size and/or optimization of performance of logiccircuits in the logic area.

SUMMARY

The inventive concept provides an image sensor, such as a complementarymetal-oxide semiconductor (CMOS) image sensor (CIS), with a simplifiedstacked structure and improved operation characteristics.

According to an aspect of the inventive concept, there is provided acomplementary metal-oxide semiconductor (CMOS) image sensor (CIS)including an upper chip, in which a plurality of pixels are arranged ina two-dimensional array structure; and a lower chip, which is below theupper chip and includes a logic region having arranged therein logiccircuits and a memory region having embedded therein a magnetic randomaccess memory (MRAM), wherein the MRAM is configured to operate as imagebuffer memory for storing image data processed by the logic region.

According to another aspect of the inventive concept, there is provideda complementary metal-oxide semiconductor (CMOS) image sensor (CIS)including an upper chip, in which a plurality of pixels are arranged ina two-dimensional array structure, color filters and micro-lenses arearranged above the pixels, and first wire layers are arranged below thepixels, wherein each of the plurality of pixels includes a photodiodeand pixel transistors; and a lower chip, which is below the upper chipand includes a logic region having arranged therein logic circuits andsecond wire layers and a memory region having disposed therein amagnetic random access memory (MRAM) adjacent to the logic region,wherein the first wire layers are electrically connected to the secondwire layers, and the MRAM is configured to operate as image buffermemory for storing image data processed by the logic region.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the inventive concept will be more clearlyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings in which:

FIG. 1 is an exploded perspective view of a complementary metal-oxidesemiconductor (CMOS) image sensor (CIS) according to an exampleembodiment, in which an upper chip in which pixels are arranged and alower chip in which logic circuits are arranged are separately shown;

FIG. 2 is a schematic diagram showing a two-dimensional array structureof pixels arranged in the upper chip in the CIS of FIG. 1 and peripheralcircuits according to an example embodiment;

FIGS. 3A and 3B are a circuit diagram and a corresponding schematic planview of a unit pixel constituting each of the pixels of FIG. 2 accordingto an example embodiment;

FIG. 4 is a schematic diagram showing a logic area and a memory area inthe lower chip in the CIS of FIG. 1 according to an example embodiment;

FIG. 5 is a cross-sectional diagram showing a logic area and a memoryarea in the lower chip of FIG. 4 according to an example embodiment;

FIGS. 6A and 6B are circuit diagrams of an MRAM cell array disposed in amemory area in the lower chip of FIG. 4 according to an exampleembodiment;

FIGS. 7A to 7D are schematic diagrams showing various exampleembodiments of a MTJ structure included in MRAM;

FIGS. 8A and 8B are an exploded perspective view and a cross-sectionalview of a structure in which an upper chip and a lower chip are bondedto each other using a through silicon via (TSV) according to an exampleembodiment of the inventive concept, and FIG. 8C is a cross-sectionalview of a structure in which an upper chip and a lower chip are bondedto each other, including additional details;

FIGS. 9A and 9B are an exploded perspective view and a cross-sectionalview of a CIS according to an example embodiment of the inventiveconcept, the CIS having a structure in which an upper chip and a lowerchip are bonded to each other via Cu—Cu direct bonding; and

FIG. 10 is a block diagram of a CIS according to an example embodimentof the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1 is an exploded perspective view of a complementary metal-oxidesemiconductor (CMOS) image sensor (CIS) according to an exampleembodiment. The CIS of FIG. 1 comprises an upper chip 100 includingpixels and a lower chip 200 including logic circuits. Chips 100 and 200are shown spaced apart for purposes of illustration.

In the CIS 1000 according to the present embodiment, the upper chip 100comprises a plurality of pixels arranged in a two-dimensional arraystructure (to be described below in more detail with reference to FIGS.2 through 3B). The lower chip 200 comprises a logic area (210 in FIG. 4) and a memory area (220 in FIG. 4 ). The lower chip is electricallyconnected to the upper chip 100 so that pixel signals from the upperchip 100 may be transferred to logic circuits of the logic area 210 ofthe lower chip 200. The stacked structure of the upper chip 100 and thelower chip 200 will be described below in more detail with reference toFIGS. 8A through 9B.

The logic circuits may be arranged in the logic area 210 of the lowerchip 200. The logic circuits may constitute various circuits forprocessing pixel signals received from pixels. For example, the logiccircuits may constitute an analog signal processing circuit, ananalog-to-digital converter (ADC) circuit, an image signal processingcircuit, and a control circuit. However, the circuits implemented by thelogic circuits are not limited thereto.

Magnetic random access memory (MRAM) may be disposed in the memory area220. Specifically, a plurality of MRAM cells may be arranged in atwo-dimensional array structure in the memory area 220. Each of the MRAMcells may include a cell transistor and magnetic tunnel junction (MTJ)structure as a unit cell. The two-dimensional array structure, the unitcell, and the MTJ structure of the MRAM cells will be described below inmore detail with reference to FIGS. 6A through 7D.

In the CIS 1000 according to the present embodiment, the MRAM of thememory area 220 may be disposed and embedded together with the logiccircuits of the logic area 210. For example, logic circuits of the logicarea 210 and the MRAM of the memory area 220 may comprise an integratedcircuit and be formed by a CMOS semiconductor manufacturing process. Theembedded form of the MRAM will be described below in more detail withreference to FIG. 5 . In FIG. 1 , the lower chip 200 is described asLogic+eMRAM, where ‘e’ of the eMRAM denotes embedded (i.e., indicatingthat the MRAM is embedded MRAM formed on and integral with the logiccircuits of logic area 210 on the same semiconductor chip).

In the CIS 1000 according to the present embodiment, the MRAM may bearranged in an embedded form in the memory area 220 of the lower chip200, and the MRAM may comprise an image buffer memory for storing frameimages. Therefore, the CIS 1000 may perform signal processing aftertemporarily storing frame images in the MRAM, thereby significantlyimproving the operation characteristics of the CIS 1000. Furthermore, inthe CIS 1000 according to the present embodiment, as the MRAM isdisposed in an embedded form together with the logic circuits of thelogic area 210, the overall manufacturing process may be simplified anda size of an entire product may be reduced (or the same size may achievebetter results). Therefore, the CIS 1000 according to the presentembodiment may be manufactured with increased yield and reduced cost.

In a CIS, data from pixels, that may be provided as pixel signals, maybe read out by driving an electronic shutter according to a drivingscheme referred to as a rolling shutter scheme. According to the rollingshutter scheme, pixel data from all pixels are not simultaneously readout, and pixel data are read out row-by-row. In addition, exposure timesof each row overlap so that, for a frame of image data (corresponding topixel data for the entire pixel array) start times and end times ofexposure of each row differ. As a result, timings for exposure andreading data of respective rows differ from one another, and when anobject moves while pixel data is being generated (via exposure of thepixels) and sequentially read row-by-row, a rolling shutter effectcausing a skewed image distorting an object image within an image framemay occur. A global shutter scheme for reducing this rolling shuttereffect has been developed by adding a circuitry that stores data foreach pixel. However, since this scheme increases the size of a CIS, itmay not be desirable for certain applications, such as a CIS for a smartphone.

In order to reduce the rolling shutter effect in the rolling shutterscheme, a scheme for reading the data of pixels of each row as quicklyas possible to reduce a time difference has been developed. However, inthe case of this scheme, since a large amount of pixel data should beread out within a short time period (to thereby reduce the deviationbetween the start and end times of the row exposures of an image frame),transmission of the pixel data must be quickly, which may require addedcomplexity to the design of an I/O unit of the CIS and an applicationprocessor (AP) receiving this pixel data, and thus using this scheme hasdifficulties in directly processing the pixel data.

The CIS 1000 according to the present embodiment may address the aboveproblems by using the MRAM as image buffer memory. For example, theabove blurring problem may be resolved by temporarily storing pixel dataas frame images in the MRAM before the pixel data is processed by theAP. As will be understood, a frame image comprises the set of pixel datafor pixels extending across the two-dimensional array for a sensed imagefor a frame period. The frame image may comprise pixel data of all ofthe pixels, of a subset thereof (e.g., when performing imagestabilization or otherwise reducing the amount of pixels correspondingto an image frame). The exposure start times of the next frame image maybe initiated before the previous frame image has been read out of theCIS 1000. Thus, the time to read out the image frame data to a sourceexternal to the CIS 1000 may be performed more slowly (e.g.,corresponding to the length of exposure time of an image frame) withoutcontributing to a rolling shutter effect. Furthermore, in the CIS 1000according to the present embodiment, since the MRAM is embedded in thelower chip 200 having arranged logic circuits therein, an additionalchip is unnecessary, and thus, the total size of the CIS 1000 may notincrease. Furthermore, since the MRAM is formed in the lower chip 200together with logic circuits via a CMOS process, the CIS 1000 accordingto the present embodiment may be manufactured via a simplifiedmanufacturing process with high yield and reduced cost.

FIG. 2 is a schematic diagram showing a two-dimensional array structureof pixels arranged in the upper chip 100 in the CIS of FIG. 1 andperipheral circuits, according to an example embodiment.

Referring to FIG. 2 , the CIS 1000 according to the present embodimentmay include a pixel unit array 100P and peripheral circuits. The pixelunit array 100P may be disposed in the upper chip 100 and a plurality ofpixels 110 may be regularly arranged in a two-dimensional arraystructure. Each of the pixels 110 may be part of a unit pixel or pixelgroup and include a photodiode and pixel transistors. The structure ofan exemplary unit pixel will be described below in more detail withreference to FIGS. 3A and 3B.

The peripheral circuits are disposed in the lower chip 200 and mayinclude a row drive circuit 40, a column signal processing circuit 50,an image buffer memory 60, an output circuit 70, and a control circuit80. The circuits of the peripheral circuits may include logic circuits(e.g., circuits formed from NAND gates, NOR gates, inverters, etc.,formed from interconnected transistors of the lower chip 200). It shouldbe appreciated that some of these or other peripheral circuits may beformed in the upper chip 100 instead of the lower chip 200.

The control circuit 80 may control overall operations of otherperipheral circuits. For example, the control circuit 80 may generateone or more clock signals and/or control signals for operating the rowdrive circuit 40 and the column signal processing circuit 50 based on amaster clock signal, and input a vertical synchronization signal, ahorizontal synchronization signal, and a master clock signal and aninput the clock signal or other control signals to the row drive circuit40 and the column signal processing circuit 50.

The row drive circuit 40 may include, for example, a shift register, andmay drive pixels row-by-row by selecting a pixel driving wire of a rowof pixels and supplying a pulse for driving the row of pixels connectedto the selected pixel driving wire or row line 150. For example, the rowdrive circuit 40 may sequentially activate the rows of pixels bysequentially and selectively providing scan pulses to the pixels 110 ofthe pixel unit array 100P row-by-row in the column-wise direction.Furthermore, upon such activation of a row of pixels by the row drivecircuit 40, pixel signals corresponding to charges generated byrespective photodiodes of the pixels 110 (e.g., during an exposureperiod corresponding to an image frame) may be provided to the columnsignal processing circuits 50 through column signal lines 120.

The column signal processing circuits 50 are arranged according torespective columns of the pixels 110 and may perform signal processing,such as noise removal, with respect to signals output from the pixels110 row-by-row for each pixel column. For example, the column signalprocessing circuit 50 may perform signal processing, such ascorrelated-double sampling (CDS), signal amplification, and A/D (analogto digital) conversion, for removing noise inherent to the pixels 110.The column signal processing circuit 50 may comprise a plurality ofsub-circuits (as shown in FIG. 2 ), each connected to a correspondingcolumn signal line 120 to perform such processing in parallel forsignals output from a row of pixels 110.

The image buffer memory 60 may include a plurality of memories 62. Eachof the memories 62 may be MRAM. The image buffer memory 60 maytemporarily store pixel signals, i.e., image data, processed by thecolumn signal processing circuit 50. Also, the image buffer memory 60may store pixel signals for each frame image.

The output circuit 70 may perform signal processing on signalssequentially transferred from the image buffer memory 60 and outputsignal-processed signals. For example, the output circuit 70 may performonly amplification or may perform various signal processing operationsother than amplification. For example, the output circuit 70 may performvarious digital signal processing operations including bad pixelcorrection (BPC), lens shading correction (LSC), black level adjustment,thermal inconsistency correction, etc. However, the signal processingfunctions of the output circuit 70 may also be performed by a processorexternal to the CIS 100, such as an application processor AP.

In the CIS 1000 according to the present embodiment, MRAM may beemployed as the image buffer memory 60. Therefore, the CIS 1000according to the present embodiment may have improved operatingcharacteristics with a smaller size, and the manufacturing processthereof may be simplified and carried out with high yield and reducedcost. For reference, a case wherein MRAM is used as the image buffermemory 60 as in the CIS 1000 according to the present embodiment may becompared with a case wherein dynamic random access memory (DRAM) orstatic random access memory (SRAM) is used as the image buffer memory60. In the case of employing DRAM, a separate chip may be necessarybecause it is difficult to embed the DRAM in a lower chip havingdisposed therein logic circuits due to its structural characteristics.Furthermore, in the case of employing SRAM, since the size of SRAM islarge, the total size of a CIS may increase.

More specifically, the SRAM has a large size as compared to MRAM,because each unit cell of the SRAM has a six-transistor (6Tr) structure(or more transistors). Furthermore, although the SRAM consumes a smallercurrent than the DRAM in a standby mode, the current consumption of theSRAM still deteriorates energy efficiency. On the contrary, in the caseof the MRAM, since a cell has a 1Tr or 2Tr structure, a size of the MRAMmay be significantly reduced since the size of each cell is reduced. Forexample, MRAM may be implemented to have a cell size from 6F² to 8F² andthus may be implemented to have a size of from about ¼ to about ⅓ ofthat of the SRAM. Here, F denotes a minimum lithographic feature size.Furthermore, in case of using the MRAM, since little standby power isconsumed, the energy efficiency may be very high.

FIGS. 3A and 3B respectively show a circuit diagram and a correspondingschematic plan view of a unit pixel constitoting each of the pixels ofFIG. 2 , according to example embodiments.

Referring to FIGS. 3A and 3B, a plurality of pixel groups SP arearranged to share certain circuitry (“SP” referring to sharing ofcertain circuitry and structure among the pixel group). In thisimplementation, each pixel group SP comprises four pixels. Theses pixelgroups SP may be arranged in a two-dimensional array structure in thepixel unit array 100P of the upper chip 100 in FIG. 2 in the CIS 1000according to the present embodiment. In FIGS. 3A and 3B, only two pixelgroups SP1 and SP2 (adjacent to each other in a first direction (anx-axis direction)) are shown in FIGS. 3A and 3B. However, as shown inFIG. 2 , in the pixel unit array 100P, the plurality of pixel groups SPare arranged in a two-dimensional array structure along both the firstdirection (the x-axis direction) and a second direction (a y-axisdirection).

In the CIS 1000 according to the present embodiment, four pixels arearranged in a pixel area PA, and transistors 114, 116, and 118 arearranged in a transistor area TA. Four pixels may constitute a singlepixel group SP and share use of transistors 114, 116 and 118. Forexample, the first pixel group SP1 may have a structure in which fourphotodiodes PD1 through PD4 surround and share one floating diffusion(FD) region 115. Furthermore, the second pixel group SP2 may also have astructure in which four photodiodes PD1 through PD4 share one floatingdiffusion FD area 115. Each floating diffusion FD area may be separatefrom other floating diffusion FD areas. In the CIS 1000 according to thepresent embodiment, one pixel may be formed using only one photodiode.Therefore, unless otherwise stated, a photodiode will be understood tocorrespond to a pixel will be described below accordingly.

In the pixel group SP, the one FD area 115 may be shared by the fourphotodiodes PD1 through PD4 via the transfer transistors 112respectively corresponding to the photodiodes PD1 through PD4, as shownin the circuit diagram of FIG. 3A. Specifically, a first transfertransistor 112-1 corresponding to the first photodiode PD1, a secondtransfer transistor 112-2 corresponding to the second photodiode PD2, athird transfer transistor 112-3 corresponding to the third photodiodePD3, and a fourth transfer transistor 112-4 corresponding to the fourthphotodiode PD4 may share the FD area 115 as a common drain region.

In addition to the four photodiodes PD1 through PD4 sharing the same FDarea 115, the four photodiodes PD1 through PD4 of a pixel group SP mayshare the transistors 114, 116, and 118. In this example, the fourphotodiodes PD1 through PD4 constituting the pixel group SP may share areset transistor 114, a source follower transistor 116, and a selectingtransistor 118. The reset transistor 114, the source follower transistor116 and the selecting transistor 118 may be arranged along the seconddirection (the y-axis direction) in the transistor area TA. The resettransistor 114 may be activated to reset the floating charge accumulatedby the photodiodes PD1 through PD4 connecting the photodiodes PD1through PD4 to the power supply Vdd removing all integrated charge fromthe previous exposure period. Source follower transistor 116 provides ananalog pixel signal to column signal line 120 corresponding to thecharge accumulated by a selected photodiode PD1 through PD4, (asselected by row line 150). Select transistor 118 operates to connect theanalog pixel signal provided by the source follower transistor 116 tothe corresponding column signal line 120. The transfer transistors 112,the reset transistor 114, the source follower transistor 116 and theselecting transistor 118 of each pixel group SP may be considered partof the pixel unit array and integrated within the upper chip 100. Inthis example, each pixel group SP may have transfer transistors 112, thereset transistor 114, the source follower transistor 116 and theselecting transistor 118 that are not shared with other pixel groups110.

Referring to the circuit diagram of FIG. 3A for a connectionrelationship between the transistors 112, 114, 116, and 118, the fourphotodiodes PD1 through PD4 may be connected to source regions of thecorresponding four transfer transistors 112. Drain regions of thetransfer transistors 112 may be connected to a source region of thereset transistor 114. The common drain region of the transfertransistors 112 may correspond to the FD area 115. The FD region 115 maybe connected to a gate electrode of the source follower transistor 116via a wire 119, in other words, a source follower gate electrode FG anda source region of the reset transistor 114. The reset transistor 114and the source follower transistor 116 may share same drain region thatmay be connected to a power supply voltage V_(DD). A source region ofthe source follower transistor 116 may be shared with the selectingtransistor 118 and a drain region of the selecting transistor 118 may beshared with the source follower transistor 116 and a source region ofthe selecting transistor 118 may be connected to the column signal line120. The voltage of the source region of the selecting transistor 118may be output to the column signal line 120 as an output signal.

In the CIS 1000 according to the present embodiment, a unit pixelconstituting the pixels 110 of the pixel unit array 100P of the upperchip 100 includes four shared pixels and the corresponding transistors114, 116, and 118 in the transistor area TA. Furthermore, a unit pixelmay include the transfer transistors 112 in correspondence to a numberof shared photodiodes. The transistors 114, 116 and 118 of thetransistor area TA and the transfer transistors 112 are referred to aspixel transistors.

In the CIS 1000 according to the present embodiment, the structure of aunit pixel is formed by a pixel group SP of the pixel unit array 100P ofthe upper chip 100, but may vary from this particular implementation.For example, in the CIS 1000 according to the present embodiment, theunit pixel constituting the pixel group SP of the pixel unit array 100Pof the upper chip 100 may have various structures, e.g., a structureincluding one photodiode (of one photodiode) and pixel transistorscorresponding thereto, a 2-shared pixel structure including twophotodiodes (of two pixels) and pixel transistors corresponding thereto,an 8-shared pixel structure including 8 photodiodes (of 8 pixels) andpixel transistors corresponding thereto, etc.

FIG. 4 is a schematic diagram showing a logic area and a memory areadisposed on a lower chip 200 in the CIS 1000 of FIG. 1 , according to anexample embodiment.

Referring to FIG. 4 , the lower chip 200 may include logic area 210 andmemory area 220. A plurality of logic circuits are arranged in the logicarea 210. As will be appreciated, the logic area 210 may be subdividedinto small areas in correspondence to respective circuits.

MRAM may be disposed in the memory area 220, and the MRAM may beembedded in the lower chip 200. For example, the logic circuits of thelogic area 210 and the MRAM of the memory area 220 may be disposedtogether in the lower chip 200 and manufactured from a CMOSmanufacturing process. For example, both the MRAM of the memory area 220and the logic circuits of the logic area 210 may be formed fromtransistors formed with the same semiconductor substrate cut from asemiconductor wafer (e.g., source/drain regions of transistors of theMRAM of the memory area 220 and the logic circuits of the logic area 210may be formed in the same semiconductor crystalline substrate).

In FIG. 4 , although the memory area 220 is shown as being disposed onthe lower right portion of the lower chip 200, the position of thememory area 220 is not limited thereto. For example, the memory area 220may be located at any portion of the lower chip 200 and/or may bedivided into several discrete sections. In the structure in which theupper chip 100 and the lower chip 200 are stacked, since the wiring ofthe upper chip 100 and the wiring of the lower chip 200 need to beelectrically connected to each other, the memory area 220 may bedisposed at a portion that does not disturb the electric connection.

Although the memory area 220 is shown as being a rectangular area, thestructure of the memory area 220 is not limited thereto. For example,the memory area 220 may have one of various structures, such as acircular structure, an elliptical structure, and polygonal structuresother than rectangular structures. A plurality of MRAM cells may bearranged in a two-dimensional array structure in the memory area 220.The two-dimensional array structure of MRAM cells will be describedbelow with reference to FIGS. 6A and 6B.

FIG. 5 is a cross-sectional diagram showing a logic area and a memoryarea in the lower chip 200 of FIG. 4 , according to an exampleembodiment. FIG. 5 depicts one segment of the layers that form a portionof the logic area and one segment of the layers that form a portion ofthe memory area. Other segments that form additional transistors and MTJstructures are not shown in FIG. 5, but some additional transistors andMTJ structures and their connections to wire layers, at least for thememory area, are shown in the circuit diagram of FIG. 6A. Logic circuitsof the logic area 210, such as a first transistor TR1, and a celltransistor TR2 of the memory area 220, may be disposed together on thesame semiconductor substrate 201 and formed through the same CMOSmanufacturing process. Semiconductor substrate may comprise acrystalline semiconductor substrate, such as a substrate cut from acrystalline bulk wafer, a SOI (silicon on insulator) wafer, etc.Furthermore, wire layers ML1, MLn−2, MLn−1, and MLn, contacts CL1, CL2,CLn−2, CLn−1, and CLn, and an Al pad PL that are disposed above thefirst transistor TR1 of the logic area 210 and wire layers MM1, MMn−1,MMn−1, and MMn, contacts CM1, CM2, CMn−2, and CMn, and an Al pad PM thatare disposed above the cell transistor TR2 may also be deposited andpatterned together through the same CMOS processes. For example,contacts of the logic area 210 and the memory area 220 that are at thesame vertical level in FIG. 5 may be simultaneously formed from the samephotoresist patterning process and same subsequent etching process.Similarly, wire layers (and wiring formed by these wiring layers) of thelogic area 210 and the memory area 220 that are at the same verticallevel in FIG. 5 may be simultaneously formed from the same metal layer(and patterned by the same metal layer patterning process, such as thesame damascene process). However, numbers and locations of wire layersand contacts of the logic area 210 may not be identical to those of thememory area 220 because the number of wire layers required by logiccircuits constituting the logic area 210 may be different from thenumber of wire layers required by elements constituting the MRAM in thememory area 220, as well as due to various design considerations.Although an interlayer insulation film 205 is shown in FIG. 5 as asingle layer on the semiconductor substrate 201, the interlayerinsulation film 205 may include various numbers of layers depending onstructures and numbers of wire layers and contacts.

In the CIS 1000 according to the present embodiment, the cell transistorTR2 and a MTJ structure 225 constituting a MRAM memory cell of thememory area 220 may be formed at the same time as when logic circuitsand wire layers of the logic area 210 are disposed. For example,elements of the cell transistor TR2 of the MRAM memory cell may beformed together when corresponding elements of transistors constitutingthe logic circuits are formed in the semiconductor substrate 201.Specifically, a device isolating area 202 and source/drain areas S/D,and gate insulation films 203, and gate electrodes 204 constituting thefirst transistor TR1 and the cell transistor TR2 may respectively beformed at the same time on the semiconductor substrate 201. It will beappreciated that when the memory cells of the memory area 220 are otherthan MRAM memory cells, the same relationships between the formation andstructure of these other memory cells and the formation and structure ofthe logic circuits may also apply as described herein with respect tothe MRAM memory cell.

The MTJ structure 225 of the MRAM may also be disposed when wire layersare disposed in the logic area 210. Specifically, when two wire layersadjacent to each other and a contact therebetween are disposed in thelogic area 210, the MTJ structure 225 of the MRAM may be disposed.However, since the structure and material of the MTJ structure 225 arecompletely different from those of a contact of the logic area 210, theMTJ structure and the logic area 210 corresponding thereto may bedisposed through separate processes. For example, when the MTJ structure225 is disposed in the memory area 220, the logic area 210 may becovered with a mask. On the contrary, when a corresponding contact isdisposed in the logic area 210, the memory area 220 may be covered witha mask.

Meanwhile, although FIG. 5 shows that the MTJ structure 225 is disposedbetween the second wire layer MMn−2 and the third wire layer MMn−1 atthe upper portion of the lower chip 200, position of the MTJ structure225 is not limited thereto. For example, the MTJ structure 225 may bedisposed anywhere between two wire layers adjacent to each other.

FIGS. 6A and 6B are circuit diagrams of an MRAM cell array disposed in amemory area in the lower chip 200 of FIG. 4 , according to an exampleembodiment.

Referring to FIG. 6A, in the CIS 1000 according to the presentembodiment, a MRAM cell array 220C1 having a two-dimensional arraystructure may be disposed in the memory area 220. The MRAM cell array220C1 may include a plurality of word lines WL, a plurality of bit linesBL, a plurality of source lines SL, and a plurality of MRAM cells Uarranged at locations where the plurality of word lines WL intersectwith the plurality of bit lines BL. The one unit cell U includes a MTJstructure MTJ 225 and a cell transistor CT and may be selected byselecting one bit line BL and one source line SL. Therefore, the MRAMcell array 220C1 according to the present embodiment may have a 1MTJ-1TRstructure. The MTJ structure 225 may basically include a pinned layer221, a tunnel layer (or a barrier layer) 222, and a free layer 223. Thespecific structure of the MTJ structure 225 will be described below inmore detail with reference to FIGS. 7A through 7D.

Regarding a connecting structure of the unit cell U, the pinned layer221 of the MTJ structure 225 may be connected to a drain of the celltransistor CT, and the free layer 223 of the MTJ structure 225 may beconnected to the bit line BL. Furthermore, a source of the celltransistor CT may be connected to the source line SL, and a gate of thecell transistor CT may be connected to the word line WL.

Alternatively, rather than MTJ structure 225, the memory cell of thememory 220 may be formed with a resistive element, such as phase changerandom access memory (PRAM) using a phase change material, or resistiverandom access memory (RRAM), using a variable resistance material like acomplex metal oxide. Furthermore, the MTJ structure 225 may also bereplaced with a resistive element of the memory 220 using aferromagnetic material. Materials constituting resistive elements mayhave resistances varying according to a magnitude and/or a direction ofa current or a voltage and may exhibit non-volatile characteristics formaintaining a resistance value even when a current or a voltage isblocked.

MRAM is a non-volatile memory device based on magneto-resistance. MRAMmay have read and write response times comparable to those of volatileRAM. For example, MRAM may be an omnipotent memory device exhibitingboth low-cost and high-capacity characteristics of DRAM, high-speedoperation characteristics of SRAM, and non-volatile characteristics offlash memory.

MRAM may be a non-volatile memory device that reads and writes datausing the MTJ structure 225 including two magnetic layers and aninsulating film interposed therebetween. The resistance value of the MTJstructure may be changed according to magnetization directions of themagnetic layers, where a difference between resistance values may beused to program data (that is, to store data) or to erase data. MRAM maychange a magnetization direction of a magnetic layer by using a spintransfer torque (STT) phenomenon.

In the MTJ structure 225, the magnetization direction of the pinnedlayer 221 may be fixed and the magnetization direction of the free layer223 may be changed by an applied program current. In other words, themagnetization directions of the two magnetic layers 221 and 223 may bearranged parallel or anti-parallel to each other as the magnetizationdirection of the free layer 223 is changed by the program current. Whenthe magnetization directions are parallel, the MTJ structure 225 may bein a low (“0”) state indicating a low resistance between the twomagnetic layers 221 and 223. When the magnetization directions areanti-parallel, the MTJ structure 225 may be in a high (“1”) stateindicating a high resistance between the two magnetic layers 221 and223. Write and read operations of MRAM may be achieved according toswitching of the magnetization direction of the free layer 223 and thehigh or low resistance state between the magnetic layers associated withthe switching of the magnetization direction of the free layer 223.

The word line WL may be enabled by the row decoder and may be connectedto a word line driver for driving a word line select voltage. The wordline select voltage activates the word line WL to perform a read orwrite operation with respect to the MTJ structure 225. The source lineSL is connected to a source line circuit. The source line circuitreceives an address signal and a read/write signal, decodes the receivedsignals, and applies a source line selection signal to the selectedsource line SL. A ground reference voltage is applied to the unselectedsource lines SL.

The bit line BL is connected to a column selecting circuit driven by acolumn selection signal. For example, a selected column select signalturns ON a column selecting transistor in the column select circuit andselects the bit line BL. The logic state of the MTJ structure 225 isoutput through a sense amplifier to the selected bit line BL through aread operation. Furthermore, a write current is transferred to theselected bit line BL through a write operation, and thus, a valuecorresponding to the logic state is stored in the MTJ structure 225.

Referring to FIG. 6B, a MRAM cell array 220C2 according to the presentembodiment may be different from the MRAM cell array 220C1 of FIG. 6A inthe connection structure of the source line SL. For example, althoughthe MRAM cell array 220C1 of FIG. 6A may have a 1MTJ-1TR structure inwhich the one cell transistor CT and the MTJ structure 225 are selectedby selecting the one bit line BL and the one source line SL, MRAM cellarray 220C2 according to the present embodiment may have a 2MTJ-2TRstructure in which the two cell transistors CT and the MTJ structure 225are selected by selecting the one bit line BL and the one source lineSL. Therefore, the source line SL of the MRAM cell array 220C2 accordingto the present embodiment may be commonly connected to sources of thetwo cell transistors CT.

Generally, the structure of the MRAM cell array 220C1 of FIG. 6A isreferred to as a separate source line structure, whereas the structureof the MRAM cell array 220C2 of FIG. 6B is referred to as a commonsource line structure.

In order to store the logic states “0” and “1” in the MTJ structure 225,which is a memory element, it is necessary for a current flowing throughthe MTJ structure 225 to be bi-directional. In other words, a currentflowing in the MTJ structure 225 when data “0” is being written shouldflow in a direction opposite to a direction in which a current flows inthe MTJ structure 225 when data “1” is being written. To implement aMRAM having a structure in which currents flow in directions opposite toeach other, the source line SL is provided in addition to the bit lineBL to change a difference between potentials of the MTJ structure 225and the cell transistor CT, and thus a direction in which a currentflows in the MTJ structure 225 may be selected.

According to connection structures of a source line and methods ofoperating the same, structures of an MRAM are categorized into theseparate source line structure and the common source line structure asdescribed above. In the case of the common source line structure, sincethe source line SL is shared by both cell transistors, common sourceline structure may be efficient in terms of a space, but the operatingvoltage thereof may be increased, because the reference voltage isapplied to the source line SL. On the other hand, in the case of theseparate source line structure, since voltages of the bit line BL andthe source line SL are interchangeable, the operating voltage of an MRAMmay be lowered. However, since it is necessary to arrange all the sourcelines SL corresponding to the bit lines BL, the separate source linestructure may be less efficient in terms of a space, that is, density.

FIGS. 7A to 7D are schematic diagrams showing various embodiments of aMTJ structure included in MRAM according to an embodiment.

Referring to FIG. 7A, the MTJ structure 225 may include the pinned layer221, the free layer 223, and the tunnel layer 222 therebetween. Themagnetization direction of the pinned layer 221 is fixed and themagnetization direction of the free layer 223 may be parallel oranti-parallel to the magnetization direction of the pinned layer 221according to data stored through a write operation. In order to fix themagnetization direction of the pinned layer 221, an anti-ferromagneticlayer may be further provided, for example.

The free layer 223 may include a material having the variablemagnetization direction. The magnetization direction of the free layer223 may be changed based on electric/magnetic factors provided outsideand/or inside a cell. The free layer 223 may include a ferromagneticmaterial including at least one of cobalt (Co), iron (Fe), and nickel(Ni). For example, the free layer 223 may include at least one selectedfrom among FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO₂,MnOFe₂O₃, FeOFe₂O₃, NiOFe₂O₃, CuOFe₂O₃, MgOFe₂O₃, EuO, and Y₃Fe₅O₁₂.

The tunnel layer 222 may have a thickness smaller than a spin diffusionlength. The tunnel layer 222 may include a non-magnetic material. Forexample, the tunnel layer 222 may be include at least one selected fromamong oxides of magnesium (Mg), titanium (Ti), aluminum (Al),magnesium-zinc (MgZn), and magnesium-boron (MgB) and nitrides oftitanium (Ti) and vanadium (V).

The pinned layer 221 may include a ferromagnetic material layer or adouble-layer structure having a ferromagnetic material layer and ananti-ferromagnetic material layer. The anti-ferromagnetic material layermay include at least one selected from among PtMn, IrMn, MnO, MnS, MnTe,MnF₂, FeCl₂, FeO, CoCl₂, CoO, NiCl₂, NiO, and Cr.

Referring to FIG. 7B, a MTJ structure 225a according to the presentembodiment has a magnetization direction perpendicular to a tunnel layer222a, and thus a direction in which a current flows and an easy axis aresubstantially parallel to each other. Such a structure having a verticalmagnetization direction is referred to as a perpendicular MTJ structure.

The vertical MTJ structure 225a also includes a pinned layer 221a, thetunnel layer 222a, and a free layer 223a. When the magnetizationdirections of the free layer 223a and the magnetization direction of thepinned layer 221a are parallel to each other, the resistance of the MTJstructure 225a may decrease. On the other hand, when the magnetizationdirection of the free layer 223a and the magnetization direction of thepinned layer 221a are anti-parallel to each other, the resistance of theMTJ structure 225a may increase. Therefore, data may be stored in thevertical MTJ structure 225a according to resistance values.

In order to implement the vertical MTJ structure 225a, the free layer223a and the pinned layer 221a may include a material having largemagnetic anisotropic energy. Examples of materials with large magneticanisotropic energy include amorphous rare earth element alloys,multilayer thin films, such as (Co/Pt)n and (Fe/Pt)n, and orderedlattice materials having an L10 crystal structure. For example, the freelayer 223a may include an ordered alloy and may include at least onefrom among iron (Fe), cobalt (Co), nickel (Ni), palladium (Pa), andplatinum (Pt). Furthermore, the free layer 223a may include at least onefrom among a Fe—Pt alloy, a Fe—Pd alloy, a Co—Pd alloy, a Co—Pt alloy,an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, and a Co—Ni—Pt alloy. These alloysmay be Fe₅₀Pt₅₀, Fe₅₀Pd₅₀, Co₅₀Pd₅₀, Co₅₀Pt₅₀, Fe₃₀Ni₂₀Pt₅₀,Co₃₀Fe₂₀Pt₅₀, or Co₃₀Ni₂₀Pt₅₀ in a chemical quantitative expression, forexample.

The pinned layer 221a may be an ordered alloy and may include at leastone from among iron (Fe), cobalt (Co), nickel (Ni), palladium (Pa), andplatinum (Pt). For example, the pinned layer 221a may include at leastone from among a Fe—Pt alloy, a Fe—Pd alloy, a Co—Pd alloy, a Co—Ptalloy, an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, and a C—Ni—Pt alloy. Thesealloys may be Fe₅₀Pt₅₀, Fe₅₀Pd₅₀, CO₅₀Pd₅₀, Co₅₀Pt₅₀, Fe₃₀Ni₂₀Pt₅₀,Co₃₀Fe₂₀Pt₅₀, or Co₃₀Ni₂₀Pt₅₀ in a chemical quantitative expression, forexample.

Referring to FIG. 7C, a MTJ structure 225′ according to the presentembodiment includes the first pinned layer 221, the first tunnel layer222, the free layer 223, a second tunnel layer 224, and a second pinnedlayer 226. Such a structure in which the tunnel layers 222 and 224 andthe pinned layers 221 and 226 are disposed at both ends around the freelayer 223 is referred to as a dual MTJ structure. Furthermore, as shownin FIG. 7C, since a horizontal magnetism is formed based on the freelayer 223, the MTJ structure 225′ according to the present embodiment isreferred to as a horizontal dual MTJ structure. A material of the firstand second pinned layers 221 and 226 may be similar to that of thepinned layer 221 of FIG. 7A, a material of the first and second tunnellayers 222 and 224 may be similar to that of the tunnel layer 222 ofFIG. 7A, and a material of the free layer 223 may be similar to that ofthe free layer 223 of FIG. 7A.

When the magnetization direction of the first pinned layer 221 and themagnetization direction of the second pinned layer 226 are fixed to beopposite to each other, magnetic forces due to the first and secondpinned layers 221 and 226 may be substantially offset. Therefore, thedual MTJ structure 225′ may perform a read operation using a smallercurrent as compared to a typical MTJ element. Furthermore, since thedual MTJ structure 225′ has a higher resistance during a read operationdue to the second tunnel layer 224, a clear data value may be obtained.

Referring to FIG. 7D, the MTJ structure 225a′ according to the presentembodiment includes the first pinned layer 221a, the first tunnel layer222a, the free layer 223a, a second tunnel layer 224a, and a secondpinned layer 226a. Since the MTJ structure 225a′ according to thepresent embodiment has a dual MTJ structure and a magnetic fieldperpendicular to the free layer 223 is formed, the MTJ structure 225a′is referred to as a vertical dual MTJ structure. A material of the firstand second pinned layers 221a and 226a may be similar to that of thepinned layer 221a of FIG. 7B, a material of the first and second tunnellayers 222a and 224a may be similar to that of the tunnel layer 222a ofFIG. 7B, and a material of the free layer 223a may be similar to that ofthe free layer 223a of FIG. 7B.

When the magnetization direction of the first pinned layer 221a and themagnetization direction of the second pinned layer 226a are fixed to beopposite to each other, magnetic forces due to the first and secondpinned layers 221a and 226a may substantially offset each other.Therefore, the dual MTJ structure 225a′ may perform a read operation viaa smaller current as compared to a typical MTJ element. Furthermore,since the dual MTJ structure 225a′ has a higher resistance during a readoperation, a clear data value may be obtained.

FIGS. 8A and 8B are respectively an exploded perspective view and across-sectional view of a structure in which an upper chip and a lowerchip are connected to each other via a through substrate vias (TSVs)according to an embodiment of the inventive concept. Each of the throughsubstrate vias (TSVs) comprise a through-hole (having a conductivewiring formed therein) extending through the substrate of a chip inwhich it is formed. Some or all of the TSVs may extend fully through theentire chip (through though the substrate and the insulating layers andconductive layers formed thereon constituting the integrated circuit ofthe chip). TSVs when implemented in a chip having a silicon substrateare referred to a through silicon vias, however the term “TSV” as usedin this application should be understood to be applicable to chipshaving substrates other than a silicon substrate.

Referring to FIGS. 8A and 8B 8A through 8C, in a CIS 1000a according tothe present embodiment, an upper chip 110a includes TSVs 130. Lower chip200a may include conductors 230. The upper chip 100a and the lower chip200a may be electrically connected to each other through electricallyconnecting pairs of the TSVs 130 and conductors 230 as shown in FIG. 8B.

More specifically, the upper chip 100a may include a center area PA anda peripheral area Peri outside the center area PA. In the center areaPA, pixels may be arranged in a two-dimensional array structure, and theplurality of first TSVs 130 may be formed in the peripheral area Peri.As shown in FIG. 8B, a semiconductor substrate 101 may be located on theupper portion of the upper chip 100a, and pixels may be disposed on thesemiconductor substrate 101. Furthermore, color filters and micro-lensesmay be disposed above the semiconductor substrate 101. On the otherhand, wire layers Mu may be disposed on the lower portion of the upperchip 100a.

The structure in which the color filters 132 and the micro-lenses 134are disposed on a surface of upper chip 100a opposite to the wire layerMu corresponding to the backside surface of the semiconductor substrate101 is shown in FIG. 8C. The backside of the semiconductor substrate 101comprises photodiodes (pixels) disposed therein. Such a structure isreferred to as a back side illumination (BSI) structure. On the otherhand, a structure in which the color filters and the micro-lenses aredisposed on the upper chip 100a on the same side of substrate 101 (thefrontside surface of substrate 101) as the wire layer Mu, that is, astructure in which color filters and micro-lenses are disposed on thewire layer Mu, is referred to as a front side illumination (FSI)structure.

In this example, the first TSV 130 is formed only in outer portions ofthree sides of the upper chip 100a and is not formed in the remainingone side. However, the arrangement structure of the first TSVs 130 isnot limited thereto. For example, the first TSV 130 may be formed in theouter portion of at least one of four sides of the upper chip 100a.Therefore, the first TSV 130 may be formed at all four sides of theupper chip 100a. The first TSV 130 may be formed to pass through theentire upper chip 100a and the first TSV 130 may be electricallyconnected to the wire layer Mu disposed in the peripheral area Peri ofthe upper chip 110a.

The lower chip 200a may also include a center area PA and a peripheralarea Peri outside the center area PA. Logic circuits and an MRAM may bearranged in the center area PA and a plurality of chip pads 230 may bearranged in the peripheral area Peri. As shown in FIG. 8B, thesemiconductor substrate 201 may be disposed at the lower portion of thelower chip 200a, and a wire layer Md may be disposed at the upperportion of the lower chip 200a. Transistors of the logic circuits andcell transistors of the MRAM may be disposed on the semiconductorsubstrate 201.

Unlike the first TSV 130, the conductors 230 may not extend through thesubstrate 201 of lower chip 200a and be formed only in the upper portionof the lower chip 200a. Conductors 230 may be electrically connected tothe wire layer Md disposed in the peripheral area Peri of the lower chip200a and be electrically connected to various circuits formed within thelower chip 200a, as discussed herein. Furthermore, as the first TSV 130and the conductors 230 are integrally connected to each other, the upperchip 100a and the lower chip 200a are electrically connected to eachother through the first TSV 130 and the conductors 230.

The first TSV 130 and the conductors 230 may be formed as an inseparableintegral structure. Each pair of a first TSV 130 and a conductor 230 maynot be separately formed in separately manufacturing the upper chip 100aand the lower chip 200a, but may be formed as a single TSV extendingfully through the upper chip 100a and fully or partially through thelower chip 200a by a TSV forming process after the upper chip 100a andthe lower chip 200a have been bonded to each other. Thus, a firstportion of conductor 230 may comprise a portion of TSV 130 that extendsinto lower chip 200a. A second portion of conductor 230 may comprise achip pad or an internal wiring pad or wiring of lower chip 200a to whichthe TSV 130 extends (TSV 130 may end at such pad/wiring of conductor 230or may extend through such pad/wiring of conductor 230).

In FIG. 8B, the dot-dashed line represents the boundary between theupper chip 100a and the lower chip 200a that are bonded to each other.Stacking and bonding of the upper chip 100a and the lower chip 200a andformation of TSVs 130 may be performed at the wafer level such that aplurality of upper chips 100a integrally formed in a first semiconductorwafer are stacked and bonded to a corresponding plurality of lower chips200a integrally formed in a second semiconductor wafer, and a pluralityof TSVs 130 are then formed in the stack of the first and second wafers.Then, each pair of the upper chip 100a and the lower chip 200a may thenbe separated from the stack of the first and second wafers into stackedchips. Of course, chip level stacking and bonding may alternatively beperformed.

In the CIS 1000 according to the present embodiment, since the first TSV130 fully penetrates through the upper chip 100a, when the first TSV 130is formed in the center area PA, a space for arranging pixels may bereduced, and thus, it may become difficult to implement a CIS with highimage quality.

FIGS. 9A and 9B are respectively an exploded perspective view and across-sectional view of a CIS according to an embodiment of theinventive concept, where the CIS has a structure in which an upper chipand a lower chip are bonded to each other using Cu—Cu direct bonding.

Referring to FIGS. 9A and 9B, in a CIS 1000b according to the presentembodiment, an upper chip 100b and a lower chip 200b are connectedwithout use of TSVs. Instead, Cu (copper) pads 140 and 240 may bedisposed on wire layers. It will be appreciated that pads 140 and 240may be formed by other conductive materials.

More specifically, the upper chip 100b has a BSI structure in which thesemiconductor substrate 101 is disposed at an upper portion of the upperchip 100b and pixels are disposed thereon. Unlike in FIG. 8A, pixels maybe arranged in a two-dimensional array structure without distinguishinga center area from a peripheral area Peri. Therefore, the upper chip100b may utilize the entire area as a pixel area, the upper chip 100bmay implement a high image quality relatively easy. On the other hand, afirst Cu pad 140 may be disposed on the wire layer Mu disposed at alower portion of the upper chip 100b. The first Cu pad 140 may beelectrically connected to the wire layer Mu and exposed from the bottomsurface of the upper chip 100b.

Since the first Cu pad 140 is exposed from the bottom surface of theupper chip 100b as shown in FIG. 9B, it may not be seen from the topsurface Since the first Cu pad 140 is disposed at the lower portion ofthe upper chip 100b and connected to internal circuitry of upper chip100b by the wire layer Mu disposed therein, the first Cu pad 140 may notinterfere with the receipt of light by photodiodes (pixels) disposed onthe upper portion of the upper chip 100b. For example, the first Cu pads140 may be disposed in the pixel area PA and overlap (having portionspositioned under) with photodiode(s). Therefore, the first Cu pad 140may be disposed anywhere in the upper chip 100b regardless of thepositions of the photodiode (pixels).

A center area and a peripheral area Peri may not be distinguished fromeach other on the lower chip 200b, and logic circuits and MRAM may bearranged across the entire lower chip 200b. As shown in FIG. 9B, thesemiconductor substrate 201 may be disposed at the lower portion of thelower chip 200b, the wire layer Md may be disposed at the upper portionof the lower chip 200b, and a second Cu pad 240 may be disposed on thewire layer Md. The second Cu pad 240 may be electrically connected tothe wire layer Mu and exposed from the top surface of the lower chip200b. Therefore, in FIG. 9A, the second Cu pad 240 is exposed from thetop surface of the lower chip 200b.

The first Cu pad 140 and the second Cu pad 240 are separately formed aspart of separate wafer processes of the upper chip 100b and the lowerchip 200b, respectively. When the upper chip 100b and the lower chip200b are stacked, the first Cu pad 140 and the second Cu pad 240 may bealigned and bonded to each other, and thus the first Cu pad 140 and thesecond Cu pad 240 may be electrically connected to each other. Theprocess for combining a Cu pad to another Cu pad is referred to as aCu—Cu direct bonding process. The Cu—Cu direct bonding process may beperformed by aligning the upper chip 100b and the lower chip 200b toarrange the first Cu pad 140 and the second Cu pad 240 to face eachother and pressing and thermally treating the same. In FIG. 9B, thedot-dashed line represents a boundary between the upper chip 100b andthe lower chip 200b. The stacking and bonding of the upper chip 100b andthe lower chip 200b through a Cu—Cu direct bonding process are alsoperformed at the wafer level, and the upper chip 100b and the lower chip200b may then be separated into stacked chips. Of course, chip levelstacking and bonding is not entirely excluded.

In the CIS 1000 according to the present embodiment, even when the upperchip 100b and the lower chip 200b are electrically connected to eachother through a Cu—Cu direct bonding and the upper chip 100b has the BSIstructure, since the first Cu pad 140 is disposed on the wire layer Muat the lower portion of the upper chip 100b, the Cu pads 140 and 240 maybe freely disposed regardless of locations of pixels. Therefore, in theCIS 1000 according to the present embodiment, a large area for arrangingpixels may be secured, and thus, thus the CIS 1000 may generate imageswith high image quality.

FIG. 10 is a block diagram of a CIS according to an embodiment of theinventive concept.

Referring to FIG. 10 , the CIS 1000 according to the present embodimentmay include the pixel array 100P, a timing generating circuit 211, ananalog signal processing circuit 213, an ADC circuit 215, MRAM 220C, asignal processing circuit 217, and a control circuit 219. The pixelarray 100P may be disposed in the upper chip 100, whereas the remainingcircuits may be disposed in the lower chip 200. The pixel array 100P maycomprise the various structures described herein, such as with respectto FIGS. 2, 3A and 3B. The timing generating circuit 211, the analogsignal processing circuit 213, the ADC circuit 215, the image signalprocessing circuit 217, and the control circuit 219 may be disposed inthe logic area 210 of the lower chip 200, such as the logic area 210 ofFIG. 4, whereas the MRAM 220C may be disposed in the memory area 220 ofthe lower chip 200 in an embedded form.

The timing generating circuit 211 may generate a timing signal, such asa clock pulse for controlling circuits, and supply the timing signal tocircuits that operate in response to the timing signal. The analogsignal processing circuit 213 may receive analog pixel signals fromselected pixels of the pixel unit 100P, each analog signal representingan intensity of light a pixel received during a frame exposure period.The analog signal processing circuit 213 may process pixel signals fromthe pixel unit 100P of the upper chip 100, and the ADC (analog todigital converter) circuit 215 may convert each of the analog signalsfrom the analog signal processing circuit 213 into a correspondingdigital signal, the set of which forming image data such as image dataof a frame corresponding to the frame exposure period. Meanwhile, theMRAM 220C may temporarily store image data from the ADC circuit 215 asframe images, the image signal processing circuit 217 may perform signalprocessing with respect to the image data from the MRAM 220C, and thecontrol circuit 219 may control the overall operations of circuits.According to an embodiment, the timing generating circuit 211 may beincluded in the control circuit 219. Also, according to an embodiment, asignal output from the image signal processing circuit 217 may betransferred to an AP through a mobile industry processor interface(MIPI), and various image signal processing (ISP) operations may beperformed at the AP.

Referring to FIG. 2 , the analog signal processing circuit 213 maycomprise correlated-double sampling (CDS) circuits and/or a signalamplifiers included in the row drive circuit 40 and the column signalprocessing circuit 50. Furthermore, the ADC circuit 215 may correspondto an AD converter included in the column signal processing circuit 50.The MRAM 220C may correspond to the image buffer memory 60, the imagesignal processing circuit 217 may correspond to the output circuit 70,and the control circuit 219 may correspond to the control circuit 80.For example, the analog signal processing circuit 213 may comprise aplurality of signal amplifiers in the row drive circuit 40, each of thesignal amplifiers may constitute a row line driver and have an outputdirectly connected to a corresponding row line 150 to activate a row ofpixels 110 connected to the row line. Each of the signal amplifiers maybe activated in sequence to output a scan pulse, the group of signalamplifiers providing scan pulses on a row-by-row basis (e.g., in acolumn-wise direction) during an exposure period to read out analogpixel signals from pixels 110 on a row-by-row basis. The analog signalprocessing circuit 213 may also comprise a plurality CDS circuitsarranged in the column signal processing circuit 50, each directlyconnected to a corresponding column signal line 120. Upon activation ofa row of pixels 110 by a signal amplifier, an analog pixel signal may beobtained by a corresponding CDS circuits connected to the pixel 110 by acorresponding column signal line 120. Column signal lines 120 and rowlines 150 may be formed by wiring layers of the upper chip 100 asdescribed herein (e.g., Mu). Row drive circuit 40 (including the signalamplifiers of the analog signal processing circuit 213) and columnprocessing circuit 50 (including CDS circuits) may be formed in thelower chip 200 in the logic area 210.

In a CIS according to the inventive concept, MRAM may be arranged in anembedded form in a memory area of a lower chip, and the MRAM may be usedas an image buffer memory for storing frame images. Therefore, the CISaccording to the inventive concept may have significantly improvedoperation characteristics due to minimization of the rolling shuttereffect by temporarily storing frame images in the MRAM and performingsignal processing.

Furthermore, in the CIS according to the inventive concept, the MRAM isdisposed in an embedded form together with logic circuits of a logicarea, and thus, the overall manufacturing process of the CIS may besimplified and the size of an entire product may be reduced. Therefore,the CIS according to the inventive concept may be manufactured withimproved yield and reduced cost.

While the inventive concept has been particularly shown and describedwith reference to the embodiments thereof, it will be understood thatvarious changes in form and details may be made therein withoutdeparting from the spirit and scope of the following claims.

What is claimed is:
 1. A complementary metal-oxide semiconductor (CMOS)image sensor (CIS) comprising: an upper chip, in which a plurality ofpixels are arranged in a two-dimensional array structure; and a lowerchip, on which the upper chip is mounted, the lower chip comprising alogic region having arranged therein logic circuits and a memory regionhaving embedded therein magnetic random access memory (MRAM), whereinone or more of the logic circuits are configured to generate image datain response to signals received from the upper chip and to operate theMRAM as an image buffer memory for storing the image data generated bythe logic region, wherein the MRAM comprises unit cells including celltransistors and magnetic tunnel junction (MTJ) structures, the unitcells being arranged in the memory region in a two-dimensional arraystructure, wherein the cell transistors are arranged on at a level thesame as a level as at which transistors of the logic region are located,wherein each MTJ structure comprises a pinned layer, a tunnel layer, anda free layer, wherein each MTJ structure is positioned between two wirelayers adjacent to each other from among a plurality of wire layersarranged above the cell transistors, and wherein the MTJ structures arepositioned between a wire layer forming a plurality of bit lines and awire layer connected to drain regions of the cell transistors.
 2. TheCIS of claim 1, wherein the CIS is configured to operate according to arolling shutter scheme for reading out data of the pixels row-by-row. 3.The CIS of claim 1, wherein the logic region comprises an analog signalprocessing circuit configured to process analog pixel signals receivedfrom the pixels of the upper chip, an analog-to-digital converter (ADC)circuit configured to convert an analog signal from the analog signalprocessing circuit into the image data, wherein the image data is adigital signal, and an image signal processing circuit configured toprocess the image data, and wherein the MRAM is configured to store theimage data and transfer the image data to the image signal processingcircuit.
 4. The CIS of claim 1, wherein the MRAM is configured to storethe image data as frame images.
 5. The CIS of claim 1, wherein aplurality of through substrate vias (TSVs) are formed in the upper chip,and wiring of the upper chip is electrically connected to wiring of thelower chip via the TSVs.
 6. The CIS of claim 1, wherein wiring of theupper chip is electrically connected to wiring of the lower chip viaCu—Cu direct bonding.
 7. The CIS of claim 1, wherein, in the upper chip,color filters and micro-lenses are formed on a backside surface of asemiconductor substrate of the upper chip, wherein wire layers arearranged on a frontside surface of the semiconductor substrate, andwherein the upper chip is stacked on the lower chip such that thebackside surface of the semiconductor substrate faces upward and thefrontside surface of the semiconductor substrate faces toward the lowerchip.
 8. A complementary metal-oxide semiconductor (CMOS) image sensor(CIS) comprising: an upper chip comprising a plurality of pixelsarranged in a two-dimensional array structure and first wire layersarranged below the pixels, wherein each of the plurality of pixelscomprises a photodiode and pixel transistors; and a lower chip on whichthe upper chip is mounted, the lower chip comprising a logic regionhaving logic circuits formed therein, second wire layers and a memoryregion having a magnetic random access memory (MRAM) cells, wherein thefirst wire layers are electrically connected to the second wire layers,and wherein the MRAM is configured to operate as an image buffer memoryfor storing image data processed by logic circuits of the logic region,wherein the MRAM comprises unit cells including cell transistors andmagnetic tunnel junction (MTJ) structures, the unit cells being arrangedin the memory region in a two-dimensional array structure, wherein thecell transistors are arranged on at a level the same as a level as atwhich transistors of the logic region are located, wherein each MTJstructure comprises a pinned layer, a tunnel layer, and a free layer,wherein each MTJ structure is positioned between two wire layersadjacent to each other from among a plurality of wire layers arrangedabove the cell transistors, and wherein the MTJ structures arepositioned between a wire layer forming a plurality of bit lines and awire layer connected to drain regions of the cell transistors.
 9. TheCIS of claim 8, wherein through substrate vias (TSVs) are formed in at aportion of the upper chip that does not include the pixels, and whereinthe first wire layers are electrically connected to the second wirelayers via the TSVs.
 10. The CIS of claim 8, wherein the first wirelayers are electrically connected to the second wire layers via Cu—Cudirect bonding.
 11. The CIS of claim 8, wherein the CIS is configured tooperate according to a rolling shutter scheme for reading out data ofthe pixels row-by-row, wherein the logic circuits constitute an analogsignal processing circuit configured to process analog pixel signalsreceived from pixels of the upper chip, an analog-to-digital converter(ADC) circuit configured to convert an analog signal from the analogsignal processing circuit into the image data, wherein the image data isa digital signal, and an image signal processing circuit configured toprocess the image data, and wherein the MRAM is configured to store theimage data and transfer the image data to the image signal processingcircuit.
 12. A CMOS image sensor comprising: a lower semiconductor chip;and an upper semiconductor chip mounted on the upper lower semiconductorchip, wherein the upper semiconductor chip comprises an array of pixels,each pixel comprising a photodiode positioned to receive light from alight source external to the CMOS image sensor and connected to a sourcefollower transistor, the source follower transistor configured toprovide an analog pixel signal corresponding to a charge accumulated bythe corresponding photodiode, a plurality of column signal lines, eachcolumn signal line connected to a column of pixels to receivecorresponding analog pixel signals, and a plurality of row lines, eachrow line connected to a corresponding row of pixels to connect each ofthe pixels of the row of pixels to a corresponding source followertransistor to provide the corresponding analog pixel signal to thecorresponding column signal line, wherein the lower semiconductor chipcomprises a logic region having arranged therein logic circuitsincluding an analog to digital converter configured to provide digitalpixel data correlated to analog pixel signals provided by the pluralityof column signal lines, and a memory region, having embedded therein amagnetic random access memory (MRAM) configured to receive and storeimage frame data resulting from the digital pixel data provide by theanalog to digital converter, wherein the MRAM comprises unit cellsincluding cell transistors and magnetic tunnel junction (MTJ)structures, the unit cells being arranged in the memory region in atwo-dimensional array structure, wherein the cell transistors arearranged on at a level the same as a level as at which transistors ofthe logic region are located, wherein each MTJ structure comprises apinned layer, a tunnel layer, and a free layer, wherein each MTJstructure is positioned between two wire layers adjacent to each otherfrom among a plurality of wire layers arranged above the celltransistors, and wherein the MTJ structures are positioned between awire layer forming a plurality of bit lines and a wire layer connectedto drain regions of the cell transistors.
 13. The CMOS image sensor ofclaim 12, wherein the lower semiconductor chip further comprises aplurality of first circuits each directly connected to a correspondingcolumn signal line.
 14. The CMOS image sensor of claim 13, wherein eachof the plurality of first circuits of the lower semiconductor chipcomprise a correlated-double sampling circuit directly connected to acolumn signal line of the upper semiconductor chip and having an outputconnected to the analog to digital converter of the lower semiconductorchip.
 15. The CMOS image sensor of claim 12, wherein the lowersemiconductor chip further comprises a row driver drive circuit directlyconnected to the row lines of the upper semiconductor chip to activateselected ones of the row lines.
 16. The CMOS image sensor of claim 12,wherein the lower semiconductor chip comprises a semi-conductorsubstrate, and wherein transistors of the MRAM and transistors of theanalog to digital converter each comprise source/drain regions formedwithin the semiconductor substrate.
 17. An image sensor comprising: afirst part including a plurality of pixels, each of the plurality ofpixels including a photodiode; and a second part configured to beelectrically connected to the first part, and including a plurality ofmagnetic random access memory (MRAM) cells arranged in a two-dimensionalarray, wherein the first part is stacked on the second part, at leasttwo pixels among the plurality of pixels share a plurality oftransistors and a floating diffusion region, and the second partcomprises: a substrate including a first surface that has a first regionand a second region; a first gate and a first source/drain disposed onthe first region of the first surface of the substrate and forming afirst transistor; a second gate and a second source/drain disposed onthe second region of the first surface of the substrate and forming asecond transistor that is at a level the same as a level at which thefirst transistor is located; a first contact disposed on the firstsource/drain and disposed on the first region of the first surface ofthe substrate; a first wire layer disposed on the first contact; asecond contact disposed on the first wire layer; a second wire layerdisposed on the second contact, a width of the second wire layer beinggreater than a width of the first wire layer; a third contact disposedon the second source/drain and disposed on the second region of thefirst surface of the substrate; a third wire layer disposed on the thirdcontact; a magnetic tunnel junction (MTJ) structure disposed on thethird wire layer, and including a pinned layer, a tunnel layer and afree layer; and a fourth wire layer disposed on the MTJ structure andforming a plurality of bit lines, the third wire layer and the fourthwire layer being adjacent to each other among wire layers on the secondsource/drain.
 18. The image sensor of claim 17, wherein a width of alower portion of the first contact is less than a width of an upperportion of the first contact, and a width of a lower portion of thethird contact is less than a width of an upper portion of the thirdcontact.
 19. The image sensor of claim 17, wherein the first region ofthe first surface of the substrate is a logic region, and the secondregion of the first surface of the substrate is a memory region.
 20. Theimage sensor of claim 17, wherein four pixels among the plurality ofpixels share the plurality of transistors and the floating diffusionregion.
 21. The image sensor of claim 17, wherein the plurality oftransistors include: a reset transistor configured to reset floatingcharge; a source follower transistor configured to provide an analogpixel signal to a column signal line; and a select transistor configuredto connect the analog pixel signal to the column signal line.
 22. Theimage sensor of claim 17, wherein the first wire layer is on the samelevel as the third wire layer, and the second wire layer is at the samevertical level as the fourth wire layer.
 23. The image sensor of claim17, wherein the second part further comprises: a fifth contact disposedon the second wire layer; a fifth wire layer disposed on the fifthcontact; a fourth contact disposed on the fourth wire layer; and a sixthwire layer disposed on the fourth contact.
 24. The image sensor of claim17, wherein the MTJ structure is at least partially overlapped with thethird contact.
 25. The image sensor of claim 17, wherein the pinnedlayer includes PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO,NiCl2, NiO or Cr, the tunnel layer includes magnesium (Mg), titanium(Ti), aluminum (Al), magnesium-zinc (MgZn), magnesium-boron (MgB),titanium (Ti) or vanadium (V), and the free layer includes cobalt (Co),iron (Fe), nickel (Ni), FeB, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2,MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO or Y3Fe5O12. 26.The image sensor of claim 17, wherein the first part and the second partare connected to each other via a through substrate via (TSV).
 27. Theimage sensor of claim 17, wherein the first part and the second part arebonded to each other using Cu—Cu direct bonding.
 28. The image sensor ofclaim 17, wherein color filters and micro-lenses are disposed on a firstsurface of a substrate of the first part, wire layers of the first partare arranged on a second surface of the substrate of the first part, andthe second surface of the substrate of the first part faces toward thesecond part.
 29. The image sensor of claim 17, wherein the image sensoris configured to operate according to a rolling shutter scheme forreading out data of the plurality of pixels row-by-row.
 30. The imagesensor of claim 17, wherein the second part includes: a row drivecircuit configured to drive pixels among the plurality of pixels; acolumn signal processing circuit configured to perform a signalprocessing with respect to signals output from the plurality of pixels;an image buffer memory configured to store image data processed by thecolumn signal processing circuit, and including the plurality ofmagnetic random access memory (MRAM) cells arranged in thetwo-dimensional array; an output circuit configured to output the imagedata transferred from the image buffer memory; and a control circuitconfigured to control overall operations of the row drive circuit, thecolumn signal processing circuit, the image buffer memory and the outputcircuit by generating one or more clock signals and/or one or morecontrol signals.
 31. An image sensor comprising: a first chip includinga plurality of pixels, each of the plurality of pixels including aphotodiode; and a second chip electrically connected to the first chip,and including a plurality of magnetic random access memory (MRAM) cellsarranged in a two-dimensional array, wherein the second chip comprises:a substrate including a first surface that has a first region and asecond region; a first gate and a first source/drain disposed on thefirst region of the first surface of the substrate and forming a firsttransistor; a second gate and a second source/drain disposed on thesecond region of the first surface of the substrate and forming a secondtransistor that is at a level the same as a level at which the firsttransistor is located; a first contact disposed on the firstsource/drain and disposed on the first region of the first surface ofthe substrate; a first wire layer disposed on the first contact; asecond contact disposed on the first wire layer; a second wire layerdisposed on the second contact; a third contact disposed on the secondwire layer; a third wire layer disposed on the third contact, a width ofthe third wire layer being greater than the width of the first wirelayer; a fourth contact disposed on the second source/drain and disposedon the second region of the first surface of the substrate; a fourthwire layer disposed on the fourth contact; a fifth contact disposed onthe fourth wire layer; a fifth wire layer disposed on the fifth contact;a magnetic tunnel junction (MTJ) structure disposed on the fifth wirelayer, and including a pinned layer, a tunnel layer and a free layer;and a sixth wire layer disposed on the MTJ structure and forming aplurality of bit lines, the fifth wire layer and the sixth wire layerbeing adjacent to each other among wire layers on the secondsource/drain, wherein the first chip is stacked on the second chip. 32.The image sensor of claim 31, wherein two pixels among the plurality ofpixels share a plurality of transistors and a floating diffusion region.33. The image sensor of claim 31, wherein four pixels among theplurality of pixels share a plurality of transistors and a floatingdiffusion region.
 34. The image sensor of claim 31, wherein a width of alower portion of the first contact is less than a width of an upperportion of the first contact, and a width of a lower portion of thefourth contact is less than a width of an upper portion of the fourthcontact.
 35. The image sensor of claim 31, wherein the first region ofthe first surface of the substrate is a logic region, and the secondregion of the first surface of the substrate is a memory region.
 36. Theimage sensor of claim 31, wherein the second chip includes: a row drivecircuit configured to drive pixels among the plurality of pixels; acolumn signal processing circuit configured to perform a signalprocessing with respect to signals output from the plurality of pixels;an image buffer memory configured to store image data processed by thecolumn signal processing circuit, and including the plurality ofmagnetic random access memory (MRAM) cells arranged in thetwo-dimensional array; an output circuit configured to output the imagedata transferred from the image buffer memory; a control circuitconfigured to control overall operations of the row drive circuit, thecolumn signal processing circuit, the image buffer memory and the outputcircuit by generating one or more clock signals and/or one or morecontrol signals.
 37. An image sensor comprising: a first chip includinga plurality of pixels, each of the plurality of pixels including aphotodiode; and a second chip electrically connected to the first chip,and including a row drive circuit, a column signal processing circuit,an image buffer memory, an output circuit and a control circuit, whereinthe row drive circuit is configured to drive pixels among the pluralityof pixels, the column signal processing circuit is configured to performa signal processing with respect to signals output from the plurality ofpixels, the image buffer memory is configured to store image dataprocessed by the column signal processing circuit, and including aplurality of magnetic random access memory (MRAM) cells arranged in atwo-dimensional array, the output circuit is configured to output theimage data transferred from the image buffer memory, the control circuitis configured to control overall operations of the row drive circuit,the column signal processing circuit, the image buffer memory and theoutput circuit by generating one or more clock signals and/or one ormore control signals, and the second chip comprises: a substrateincluding a first surface that has a first region and a second region; afirst gate and a first source/drain disposed on the first region of thefirst surface of the substrate and forming a first transistor; a secondgate and a second source/drain disposed on the second region of thefirst surface of the substrate and forming a second transistor that isat a level the same as a level at which the first transistor is located;a first contact disposed on the first source/drain and disposed on thefirst region of the first surface of the substrate; a first wire layerdisposed on the first contact; a second contact disposed on the firstwire layer; a second wire layer disposed on the second contact; a thirdcontact disposed on the second wire layer; a third wire layer disposedon the third contact; a fourth contact disposed on the secondsource/drain and disposed on the second region of the first surface ofthe substrate; a fourth wire layer disposed on the fourth contact; afifth contact disposed on the fourth wire layer; a fifth wire layerdisposed on the fifth contact; a magnetic tunnel junction (MTJ)structure disposed on the fifth wire layer, and including a pinnedlayer, a tunnel layer and a free layer, the MTJ structure directlycontacting the fifth wire layer; and a sixth wire layer disposed on theMTJ structure and forming a plurality of bit lines, the sixth wire layerdirectly contacting the MTJ structure, wherein the first chip is stackedon the second chip.
 38. The image sensor of claim 37, wherein a width ofthe second wire layer is greater than a width of the first wire layer, awidth of the third wire layer is greater than the width of the secondwire layer, a width of the fifth wire layer is greater than a width ofthe fourth wire layer, and a width of the sixth wire layer is greaterthan the width of the fifth wire layer.
 39. The image sensor of claim37, wherein at least two pixels among the plurality of pixels share aplurality of transistors and a floating diffusion region.
 40. The imagesensor of claim 37, wherein four pixels among the plurality of pixelsshare a plurality of transistors and a floating diffusion region.